Silicon Process Integration Engineer, Korea

소개

Tesla is looking for process integration engineer to enable advanced logic SOC's. In this highly visible role, you will work with cross functional teams and foundry integration teams in developing next generation custom SOCs for Tesla's current and future platforms. You will be involved in NPI, high volume manufacturing, process window characterization, yield improvement, process optimization, WAT analysis, reliability projections, skew methodologies, product qualification, DPPM reductions.

주요업무

• Lead and coordinate joint technical efforts with the foundry to resolve complex process-related issues that impact product performance or yield. • Drive Foundry process integration teams in bringing up the processes for advanced technology nodes (GAA and beyond). • Collaborate with cross functional teams in optimizing power, performance, area, cost, etc for future SOC's. • Debug process related issues in advanced technology nodes: FinFET, GAA, Back Side Power Delivery Network(BSPDN) and beyond. • Continuously monitor and analyze foundry process data to ensure the health of the manufacturing line and to identify and troubleshoot issues related to yield, performance, and reliability. • Improve product yield by optimizing processes without impacting reliability and performance. • Qualify processes which can create long term impact in scaling Tesla's products while reducing costs. • Drive qualified processes in reducing defects and sustain high volume manufacturing at reduced auto grade PPM levels. • Lead structured DOE for yield, reliability and process window characterization.

자격요건

• BS/MSEE/Ph.D. with minimum 10 years of experience in process development, yield improvement, foundry and vendor management. • Strong background in optimizing silicon processes (FEOL, MOL, BEOL) for advanced technology nodes (FinFET, GAA, BSPDN). • Hands on experience in debugging process related issues impacting yield, reliability, power, performance, cost and area. • In-depth understanding in device physics, device level reliability, process qualification, physical failure analysis, statistical analysis. • Good background in design technology co-optimization (DTCO) for advanced nodes. • Ability to resolve ambiguity and adapt to fast paced environment. • Effective communication and ability to work with geographically distributed teams. • Expected travel is 25% of time.

우대사항

• Experience in collaborating with external vendors and incorporating cutting edge processes into products is highly desired.

혜택 및 복지

자세한 사항은 홈페이지 참조